This invention is applicable to data processing systems with second level (L2) memory used for both unified (data and instructions) level two cache and flat (L2 SRAM) memory used to hold critical data and instructions. The second level memory (L2) directly addressable SRAM memory is accessible by both external and internal direct memory access (DMA) units.
In the applicable digital data processor all CPU activity is in multiples of cache lines. The level one instruction cache line size is 32 bytes. The level one data cache line size is 64 bytes. The level two cache line size is 128 bytes. The L2 memory controller should be able to handle this traffic efficiently to ensure high throughput and reduced latency for CPU traffic.